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Design and Characterization Methodology for Efficient Wide Range Tunable MEMS Filters
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A Low-Offset Sense Amplifier with Self-Adaptive Calibration and Dynamic Body-Biased Mitigation Technology for

Yulan Liu1,2, Yibo Hu1, Han Xiao1,2

  • 1State Key Laboratory of Materials for Integrated Circuits, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China.

Micromachines
|May 27, 2026
PubMed
Summary
This summary is machine-generated.

This study introduces SC-DISBSA, a novel sense amplifier (SA) that significantly reduces offset voltage (VOS) in SRAM. This innovation enhances read reliability and power efficiency for static random-access memory (SRAM) devices.

Keywords:
body biasoffset calibrationsense amplifier (SA)static random-access memory (SRAM)threshold voltage mismatch

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Area of Science:

  • Integrated Circuit Design
  • Semiconductor Device Physics

Background:

  • Offset voltage (VOS) is a critical parameter in sense amplifiers (SAs) affecting SRAM read reliability and performance.
  • Existing sense amplifier designs often struggle with significant VOS, leading to suboptimal SRAM operation.

Purpose of the Study:

  • To propose and evaluate SC-DISBSA, a novel low-VOS sense amplifier.
  • To demonstrate the effectiveness of combining self-adaptive calibration with dynamic body bias technology for VOS reduction.

Main Methods:

  • Developed a three-step self-adaptive calibration algorithm based on the linear relationship between transfer gate voltage and VOS.
  • Utilized dynamic body bias technology to further suppress remaining variations.
  • Implemented a calibration control circuit for quantitative mismatch calibration.

Main Results:

  • SC-DISBSA achieved a VOS standard deviation (σOS) below 3.1 mV across a 0.7 V to 1.1 V supply range in a 28 nm CMOS process.
  • Demonstrated significant reductions in σOS: 49.9% vs. VLSA and 69.3% vs. CLSA.
  • Reduced bitline discharge delay by 51.7% and improved average read sensing power by 24.9% compared to VLSA.
  • Decreased worst-case static power by 36.8% and gate area by 18.9% relative to VLSA.

Conclusions:

  • SC-DISBSA effectively minimizes offset voltage in sense amplifiers.
  • The proposed SA design optimizes SRAM read latency and power efficiency.
  • This approach offers a promising solution for high-performance and reliable SRAM.