An Embedded Trace Redistribution Layer with Rounded-Bottom Cu Geometry and Ti Capping for Enhanced Electromigration...

Area of Science:

• Materials Science
• Electrical Engineering
• Semiconductor Device Physics

Background:

• Electromigration (EM) is a critical reliability challenge in advanced semiconductor interconnects.
• Current reliability enhancement strategies often involve complex process modifications or material additions.

Purpose of the Study:

• To evaluate the electromigration (EM) performance of a novel embedded trace redistribution layer (ETR) design.
• To compare the EM reliability of the ETR with a conventional semi-additive-process (SAP) redistribution layer (RDL).
• To elucidate the mechanisms behind the improved EM performance of the ETR.

Main Methods:

• Comparative analysis of ETR (with and without Ti capping) and SAP RDL under EM stress conditions.
• Transmission electron microscopy (TEM) with atomic-percentage mapping to assess barrier effectiveness.
• Electro-thermal and stress simulations to identify failure mechanisms and stress concentrations.

Main Results:

• The ETR demonstrated a marked improvement in EM lifetime compared to the SAP RDL.
• The Ti-capped ETR showed minimal resistance increase (<10%) after 4000 hours of testing.
• TEM confirmed Ti capping effectively prevented copper diffusion.

Conclusions:

• The novel ETR design, featuring rounded-bottom copper traces and Ti capping, significantly enhances EM reliability.
• The rounded-bottom geometry mitigates stress concentration, while Ti capping acts as an effective diffusion barrier.
• These findings offer a promising approach for improving the long-term stability of semiconductor interconnects.