Design of a Compact Two-Stage ADC Based on a Nonuniform Flash Architecture for NTC Thermistor Linearization

Area of Science:

• Electrical Engineering
• Signal Processing
• Instrumentation

Background:

• Sensor linearization is crucial for accurate data acquisition, especially with nonlinear sensors like thermistors.
• Conventional two-stage linearizing ADCs often suffer from high circuit complexity and component count.
• Addressing these challenges requires innovative ADC architectures for improved efficiency and performance.

Purpose of the Study:

• To propose a compact two-stage analog-to-digital converter (ADC) that effectively linearizes sensor outputs.
• To reduce circuit complexity and component count compared to traditional two-stage linearizing ADCs.
• To maintain high resolution and nonlinearity reduction for improved measurement accuracy.

Main Methods:

• A nonuniform flash ADC is leveraged within a two-stage architecture to perform sensor linearization.
• Circuit compactness is achieved by reducing comparators and reusing the flash ADC across stages.
• Nonuniform quantization is implemented using a reference resistor ladder with varied resistance values to approximate the inverse of the input signal.

Main Results:

• The proposed two-stage ADC significantly reduces component count: nearly 75% fewer comparators and 50% fewer resistors.
• LabVIEW simulations using an NTC thermistor demonstrate substantial error reduction from 1 °C to 0.0033 °C.
• An overall resolution of 20 bits is achieved using a 10-bit nonuniform flash ADC, validating the linearization effectiveness.

Conclusions:

• The proposed compact two-stage ADC architecture offers an efficient solution for sensor linearization challenges.
• This approach effectively reduces circuit complexity while preserving high resolution and nonlinearity correction.
• The demonstrated performance validates the potential of nonuniform quantization for accurate sensor data acquisition.