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Related Experiment Video

Updated: May 28, 2026

An Experimental Protocol for Femtosecond NIR/UV - XUV Pump-Probe Experiments with Free-Electron Lasers
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An Experimental Protocol for Femtosecond NIR/UV - XUV Pump-Probe Experiments with Free-Electron Lasers

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An FPGA-Based Event-Timing Front-End for Time-Resolved Sensing with Dual-Mode Experimental Characterization.

Juan Núñez1, Rafaella Fiorelli1

  • 1Instituto de Microelectrónica de Sevilla, IMSE-CNM (CSIC/Universidad de Sevilla), Américo Vespucio 28, 41092 Sevilla, Spain.

Sensors (Basel, Switzerland)
|May 27, 2026
PubMed
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This FPGA-based timing front-end offers reliable event detection for time-resolved sensing. It balances performance and data export, providing a practical solution for asynchronous workflows.

Area of Science:

  • Electronics Engineering
  • Instrumentation
  • Digital Systems

Background:

  • Time-resolved sensing and event-driven measurements require precise timing.
  • Existing systems face challenges with event trustworthiness, dead-time, and data readout.

Purpose of the Study:

  • To present an FPGA-based timing front-end for detector-independent use.
  • To evaluate its performance in asynchronous time-resolved sensing workflows.

Main Methods:

  • Implemented a timing subsystem with carry-chain interpolation and timestamp formation.
  • Validated using internal ILA and external UART-based experiments.
  • Assessed event quality, dead-time handling, and host-visible export.

Main Results:

Keywords:
FPGA TDCSPAD-based sensing workflowscoarse–fine timestampingdetector-independent timing subsystemevent qualificationevent timingtime-resolved sensingtime-to-digital convertertiming front-end

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  • Identified a safe operating point for export-compatible data acquisition.
  • Characterized a high-rate regime and the transition between modes.
  • Demonstrated practical behavior without catastrophic degradation across frequencies.

Conclusions:

  • The FPGA timing front-end is a practical, experimentally characterized subsystem.
  • It offers interpretable behavior in internal and export-visible operating regimes.
  • Suitable for asynchronous workflows like single-photon avalanche diode (SPAD) sensing.