A fully-CMOS spiking LIF neuron implementation for optimized STDP learning on memristor.

Area of Science:

• Neuromorphic Engineering
• Integrated Circuit Design
• Computational Neuroscience

Background:

• The demand for faster, energy-efficient computing drives neuromorphic hardware development.
• Spiking neural networks (SNNs) offer event-driven, parallel processing suitable for these demands.
• Efficient implementation of synaptic learning, like spike-timing-dependent plasticity (STDP), is a key challenge in hardware SNNs.

Purpose of the Study:

• To propose a novel CMOS leaky integrate-and-fire (LIF) neuron design.
• To enable local, on-chip STDP-like learning with memristive synapses.
• To reduce circuit complexity and energy overhead for synaptic learning in SNN hardware.

Main Methods:

• A fully CMOS LIF neuron was designed to generate bipolar output spikes.
• The neuron operates in distinct training and inference modes for optimized function.
• A 15x4 SNN with a winner-takes-all (WTA) mechanism was implemented and simulated in 65-nm CMOS technology.

Main Results:

• The proposed neuron successfully enabled local, on-chip STDP-like learning with memristive synapses.
• The design demonstrated stable neuron operation under process variations.
• The SNN proof-of-concept achieved successful pattern association, with fast training (0.6 ms) and inference (0.32 ms) times per pattern.

Conclusions:

• The developed CMOS LIF neuron effectively supports on-chip synaptic plasticity for neuromorphic SNNs.
• The dual-mode operation enhances efficiency for both learning and inference.
• This design presents a promising approach for energy-efficient, high-performance neuromorphic computing hardware.