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Hybrid approximate multiplier architectures for low power DWT image compression.
R Anitha1, Sriadibhatla Sridevi2
1Department of Micro & Nanoelectronics, School of Electronics Engineering, Vellore Institute of Technology, Vellore, TamilNadu, India.
Scientific Reports
|June 4, 2026
Summary
This study introduces an energy-efficient image compression method using approximate computing and hybrid multipliers in the discrete wavelet transform (DWT). The approach significantly reduces power and hardware usage without compromising visual quality.
Area of Science:
- Computer Engineering
- Digital Signal Processing
Background:
- Approximate computing offers energy efficiency for error-tolerant applications like image compression.
- Traditional computing methods can be power-intensive for complex tasks.
Purpose of the Study:
- To develop a high-efficiency image compression architecture using approximate multipliers.
- To reduce delay, power consumption, and hardware resources in image compression pipelines.
Main Methods:
- Implemented four approximate variants of discrete wavelet transform (DWT) using hybrid Wallace, Dadda, and Baugh-Wooley multipliers.
- Applied approximation to less significant bits while maintaining precision in more significant bits for visual accuracy.
- Conducted hardware performance analysis using FPGA synthesis on the Artix-7 platform.
Main Results:
- The fourth approximate DWT variant demonstrated significant improvements.
- Achieved a Peak Signal-to-Noise Ratio (PSNR) of 35.9 dB, a Structural Similarity Index Measure (SSIM) of 0.94, and a compression ratio of 1.9.
- Error analysis confirmed minimal deviation between original and reconstructed images.
Conclusions:
- Strategic approximation in computational stages enables energy-efficient wavelet-based image compression.
- The proposed method achieves substantial energy savings without noticeable loss in perceptual quality.
- The hybrid approximate multiplier approach is effective for optimizing hardware resource usage and performance.
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