Efficient FPGA accelerator for low-power high-speed BCI motor imagery classification using novel deep learning

Area of Science:

• Neuroscience
• Computer Science
• Machine Learning

Background:

• Brain-computer interfaces (BCIs) facilitate direct communication between the brain and external devices.
• Electroencephalography (EEG) is a common BCI signal source but suffers from noise and instability.
• Deep learning (DL) models are needed for automated motor imagery (MI) classification from complex EEG data.

Purpose of the Study:

• To develop an automated, accurate, and efficient DL system for MI classification using EEG signals.
• To address challenges in EEG data processing, including low signal-to-noise ratio and high dimensionality.
• To enable real-time deployment of DL models on low-power edge devices.

Main Methods:

• A novel Few-Shot Learning (FSL)-Dual Attention-based SqueezeNet (FSL-DAM-SqueezeNet) DL model was designed.
• FSL was employed to enhance learning from limited data and improve generalization.
• A hardware accelerator was developed for efficient, low-power edge deployment.

Main Results:

• The FSL-DAM-SqueezeNet achieved high accuracies: 97.04% (intra-session), 87.02% (cross-subject), and 95.68% (inter-session) on the BCI Competition IV 2a dataset.
• The model demonstrated over 98% accuracy across multiple public datasets, indicating strong generalizability.
• The hardware accelerator achieved low power consumption (12.14 W) and fast MI classification (5.01 ms).

Conclusions:

• The proposed FSL-DAM-SqueezeNet offers a robust solution for accurate EEG-based MI classification.
• The integrated hardware accelerator enables efficient, real-time BCI applications on edge devices.
• This framework significantly advances the practical application of BCIs in various domains.