Efficient FPGA accelerator for low-power high-speed BCI motor imagery classification using novel deep learning

A brain-computer interface (BCI) is an advanced technology that enables direct communication between the human brain and external systems, eliminating the need for intermediaries. Electroencephalography (EEG) is a commonly used signal for developing BCIs. However, EEG signals have challenges such as a poor signal-to-noise ratio, high dimensionality, nonlinearity, and instability. This necessitates the development of an automated system using deep learning (DL) models for motor imagery (MI) classification. Many researchers have worked on MI classification and developed various algorithms; however, several issues remain unsolved, including achieving high accuracy for EEG data across all groups and unseen data, effective feature extraction, and deploying DL models on edge devices with low power consumption and high-speed MI classification. To address these challenges, a novel DL model, Few-Shot Learning (FSL)-Dual Attention-based SqueezeNet, is designed and tested. FSL enables learning MI classification with a small amount of data and improves accuracy on unseen data. SqueezeNet, combined with a Dual Attention Mechanism (DAM), effectively extracts important temporal and frequency features from EEG signals with low computational cost. The proposed network is evaluated on the BCI Competition IV 2a dataset under intra-session, cross-subject, and inter-session settings. It achieves accuracies of 0.9704, 0.8702, and 0.9568, respectively, outperforming well-known DL models such as EfficientNet (0.9426 in intra-session). Further comparisons with existing methods demonstrate competitive and consistent performance across different evaluation protocols. For generalizability analysis, the proposed network is tested on other public datasets. The proposed network achieves an accuracy of over 98% across all datasets, proving its effectiveness for MI classification using EEG signals. Next, a hardware accelerator is designed to deploy the proposed network on edge devices. The hardware is optimized for fast MI detection and low power consumption by employing a dual-core DPU and a dual-buffer scheme. The proposed accelerator's performance and hardware utilization are analyzed. The hardware design consumes only 12.14 W, which is 4.8 and 6.3 times lower than CPU and GPU power consumption, respectively. It performs MI classification in just 5.01 ms, significantly faster than CPU and GPU inference times. The proposed DL network and hardware accelerator demonstrate that the framework is well-suited for real-time deployment in MI classification tasks.