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Kanagaraj Ramasamy1, Viswanathan Nallasamy2
1Department of Electronics and Communication Engineering, Mahendra Engineering College (Autonomous), Namakkal, India. Kanagaraj787@gmail.com.
Scientific Reports
|June 6, 2026
Summary
This study introduces a novel mechanism to reduce soft error rates (SER) in combinational circuits. The method combines evolutionary analysis, AIG logic, and hypergraph partitioning, achieving a 23.7% average SER decrease.
Area of Science:
- Electrical Engineering
- Computer Engineering
- Reliability Engineering
Background:
- Soft errors, caused by high-energy particles, pose a significant threat to the reliability of combinational circuits.
- These errors affect configuration bits, potentially leading to permanent functional failures despite their temporary nature.
Purpose of the Study:
- To introduce an extensive Soft Error Rate (SER) reduction mechanism for enhancing circuit reliability.
- To address the challenge of permanent functional errors caused by repetitive soft errors in configuration and routing bits.
Main Methods:
- A novel approach combining Evolutionary-based Failure Probability analysis, Application-Specific Integrated Circuit (ASIC) Implementation using And-Inverter Graphs (AIG), and multi-level hypergraph-based partitioning.
- Utilizing METIS for circuit partitioning and ABC for logical implementation.
- Focusing on continuous improvement of circuit designs to maximize SER reduction.
Main Results:
- The proposed techniques were applied to ISCAS'85 benchmark circuits.
- Achieved a significant average SER decrease of 23.7% compared to existing methods.
- Demonstrated robustness in designing complex architectures and flexible circuit designs.
Conclusions:
- The developed method offers a practical and scalable solution for reducing SER in modern integrated circuits.
- Significantly enhances circuit reliability against soft errors.
- Provides a robust approach for designing reliable digital systems.
