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Hybrid and advanced convolution techniques for highly accurate, reliable and automated ECG classification
R Gokul1, Yaswanth Sree Penumalli1, Chalamala Ranjith1
1Department of ECE, School of EEE, SASTRA Deemed University, Thanjavur, Tamilnadu, India.
Abstract:
Cardiac arrhythmias are a leading cause of cardiovascular mortality worldwide, and auto- mated analysis of electrocardiogram (ECG) recordings is an unmet clinical need. This paper introduces a hybrid 1D Convolutional Neural Network (CNN) architecture for automated ECG heartbeat classification that captures both multi-scale morphological and long-range temporal dependencies. The architecture combines Dynamic Kernel Switching (DKS) with adaptive gating over kernel sizes {3, 5, 7}, a Self-Attention module, and Dilated Convolutions at dilation rates 2 and 4. For low-power edge deployment on Neural Processing Units (NPUs) and FPGA/ASIC platforms, three quantization paths are evaluated: (1) Dynamic Post-Training Quantization (PTQ) with INT8 weights and FP32 I/O, (2) Full-Integer PTQ with INT8 weights and activations, and (3) Quantization-Aware Training (QAT). With a corrected stratified 72/8/20 train/validation/test protocol, focal loss (γ = 2.0), AdamW optimization and cosine learning rate decay, the proposed model achieves 98.99% test accuracy and a macro F1-score of 0.9484 on the MIT-BIH Arrhythmia Database (16,219 held-out test beats, five AAMI classes). Five-fold stratified cross-validation confirms statistical robustness: 98.93% ± 0.10% accuracy with 95% confidence interval [98.84%, 99.02%]. A comprehensive seven-variant ablation study covering Self-Attention, CBAM, CSA, and SimSA demonstrates that the proposed DKS + Self-Attention combination outperforms all alternatives. Generalization is further validated on five independently withheld MIT-BIH patient recordings (10,444 beats), achieving 92.86% accuracy and macro F1 of 0.8219. The model comprises only 331,733 parameters and reduces to ≈0.32 MB under Dynamic PTQ, enabling direct TFLite/INT8 conversion for RTL-level FPGA deployment.
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