Suppressing Gate-Induced Drain Leakage with an Asymmetric Gate Design in HiPco CNT FETs

Carbon nanotube field-effect transistors (CNT FETs) hold great promise for extending Moore's Law, yet their performance is critically limited by excessive off-state leakage, caused by band-to-band tunneling (BTBT) in narrow bandgap CNT channels. In this work, we overcome this long-standing bottleneck by introducing a co-design strategy that integrates a small-diameter HiPco CNT channel with a novel asymmetric gate architecture. This approach strategically reshapes the channel electrostatics to simultaneously suppress the gate-induced drain leakage (GIDL) effect and preserve excellent carrier transport. The efficacy of this strategy is rigorously validated through calibrated technology computer-aided design (TCAD) simulations for both NMOS and PMOS operation, demonstrating an ultralow off-current of 10 fA/µm, an on-current of 1.08 mA/µm, and a record on-off ratio of 1.1 × 10¹¹ for back-gated CNTFETs at the 90 nm node. The design exhibits outstanding scalability: at the scaled 28 nm node with a supply voltage of 0.7 V, the PMOS device achieves 3 mA/µm on-current and 6 pA/µm off-current, maintaining an on-off ratio of 5 × 10⁸. This work establishes a scalable pathway toward femtoampere-level CNT CMOS, addressing the static power challenge in future nano-electronics.