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Related Concept Videos

MOSFET: Enhancement Mode01:22

MOSFET: Enhancement Mode

Enhancement-mode MOSFETs are pivotal components in electronics, distinguished by their capacity to act as highly efficient switches. They are part of the larger family of metal-oxide Semiconductor Field-Effect Transistors (MOSFETs). They are available in two types: p-channel and n-channel, each tailored to specific polarity operations.
In their basic form, enhancement-mode MOSFETs are typically non-conductive when the gate-source voltage (Vgs) is zero. This default 'off' state means no current...
Metal-Semiconductor Junctions01:24

Metal-Semiconductor Junctions

The contact of metal and semiconductor can lead to the formation of a junction with either Schottky or Ohmic behavior.
Schottky Barriers
Schottky barriers arise when a metal with a work function (Φm) contacts a semiconductor with a different work function (Φs). Initially, electrons transfer until the Fermi levels of the metal and semiconductor align at equilibrium. For instance, if Φm > Φs, the semiconductor Fermi level is higher than the metal's before contact. The semiconductor's...
Types of Semiconductors01:20

Types of Semiconductors

Intrinsic semiconductors are highly pure materials with no impurities. At absolute zero, these semiconductors behave as perfect insulators because all the valence electrons are bound, and the conduction band is empty, disallowing electrical conduction. The Fermi level is a concept used to describe the probability of occupancy of energy levels by electrons at thermal equilibrium. In intrinsic semiconductors, the Fermi level is positioned at the midpoint of the energy gap at absolute zero. When...
Biasing of Metal-Semiconductor Junctions01:27

Biasing of Metal-Semiconductor Junctions

Biasing metal-semiconductor junctions involves applying a voltage across the junction. Specifically, the metal is connected to a voltage source, while the semiconductor is grounded. This technique is essential for controlling the direction and magnitude of current flow in electronic devices, including diodes, transistors, and photovoltaic cells.
In Schottky junctions, where the semiconductor is n-type, applying a positive voltage to the metal relative to the semiconductor reduces its Fermi...
MOSFET: Depletion Mode01:20

MOSFET: Depletion Mode

Depletion-mode MOSFETs represent a unique subset of MOSFET technology, functioning fundamentally differently from their enhancement-mode counterparts. Unlike enhancement MOSFETs, which require a positive gate-source voltage (Vgs) to turn on, depletion-mode MOSFETs are inherently conductive and "normally on" devices.
The primary characteristic of depletion-mode MOSFETs is their ability to conduct current between the drain and source terminals without gate bias. This inherent conductivity arises...
Biasing of FET01:22

Biasing of FET

Biasing a Junction Field Effect Transistor (JFET) is crucial for setting operational parameters and ensuring efficient functioning in electronic circuits. JFETs are characterized by using a single carrier type in N-channel or P-channel configurations, where the channel is surrounded by PN junctions. These junctions are central to the device's ability to control current flow.
In an N-channel JFET, the structure consists of N-type material forming the channel on a P-type substrate, with the gate...

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Updated: Jun 13, 2026

Electric-field Control of Electronic States in WS2 Nanodevices by Electrolyte Gating
10:36

Electric-field Control of Electronic States in WS2 Nanodevices by Electrolyte Gating

Published on: April 12, 2018

Enhancing Hole Mobility in Monolayer WSe2 p-Type Field-Effect Transistors via Process-Induced Compression.

He Lin Zhao1,2,3,4, Sheikh Mohd Ta-Seen Afrid1,3,4, Dongyoung Yoon5,2,4

  • 1Department of Electrical and Computer Engineering, University of Illinois Urbana-Champaign, Urbana, Illinois 61801, United States.

ACS Nano
|June 11, 2026
PubMed
Summary
This summary is machine-generated.

Compressive strain significantly boosts hole mobility and on-current in 2D tungsten diselenide (WSe2) field-effect transistors (FETs). This strain engineering approach enhances performance by reducing intervalley scattering, offering a powerful method for beyond-silicon electronics.

Keywords:
2D materialsWSe2first-principles simulationsmobilitystrain engineeringtransistors

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Theoretical Calculation and Experimental Verification for Dislocation Reduction in Germanium Epitaxial Layers with Semicylindrical Voids on Silicon
06:57

Theoretical Calculation and Experimental Verification for Dislocation Reduction in Germanium Epitaxial Layers with Semicylindrical Voids on Silicon

Published on: July 17, 2020

Area of Science:

  • Materials Science
  • Condensed Matter Physics
  • Nanotechnology

Background:

  • Designing advanced electronics beyond silicon requires understanding 2D material properties.
  • Heterointegrated 2D materials offer promising avenues for next-generation electronic devices.
  • Strain engineering is a key factor influencing interfacial mechanics and electrical performance.

Purpose of the Study:

  • To investigate the impact of biaxial compressive strain on the electrical performance of p-type monolayer WSe2 field-effect transistors (FETs).
  • To analyze the relationship between applied strain, interfacial mechanics, and enhanced hole mobility.
  • To explore the underlying physical mechanisms responsible for strain-induced performance improvements.

Main Methods:

  • Fabrication of monolayer WSe2 field-effect transistors (FETs).
  • Sequential deposition of AlOx to incrementally apply compressive strain to WSe2 channels.
  • In-situ photoluminescence and electrical transport measurements to track device performance under varying strain levels.
  • Combined experimental analysis with computational simulations to understand strain effects.

Main Results:

  • Significant enhancement in hole mobility, with a factor increase of 340 ± 95% per unit strain (/%ε).
  • Substantial increase in on-current, with a factor increase of 460 ± 340% per unit strain (/%ε).
  • Simulations identified reduced intervalley scattering between Γ-K valence bands as the primary mechanism for performance enhancement.

Conclusions:

  • Compressive strain is a highly effective technique for enhancing the performance of 2D p-type FETs.
  • The observed performance enhancement is robust and independent of carrier density, impurity levels, or the dielectric environment.
  • Strain engineering offers a powerful, multiplicative approach to device optimization, complementing defect and doping strategies for 2D material-based electronics.