Improving IoT Cybersecurity Performance with Lifecycle-Motivated Bit-Manipulation Compiler Optimizations

Area of Science:

• Computer Science
• Embedded Systems Engineering

Background:

• Resource-constrained IoT devices face challenges with latency, code size, and energy for cryptographic functions.
• Cryptographic primitives often involve bit-oriented operations that can be inefficiently implemented.

Purpose of the Study:

• To develop a general LLVM backend instruction-selection strategy for optimizing single-bit update idioms in cryptographic code.
• To improve the efficiency of cryptographic primitives on resource-constrained IoT devices.

Main Methods:

• Proposed a general LLVM backend instruction-selection strategy to identify and lower LOAD--(AND/OR)--STORE sequences.
• Implemented the strategy for the Renesas RL78/G23 ISA, mapping patterns to SET1/CLR1 instructions.
• Evaluated performance using cycle counts and code size on SHA-256-driven workloads.

Main Results:

• Demonstrated cycle reductions and code size improvements on the RL78/G23 platform.
• Quantified latency impact across different clocking modes by converting cycle reductions to absolute time.
• Validated the strategy on workloads including firmware integrity, hashing, authentication, and key derivation.

Conclusions:

• The proposed LLVM backend strategy effectively optimizes single-bit update idioms for cryptographic primitives on IoT devices.
• The approach shows potential for adaptation to other embedded architectures with similar bit manipulation capabilities.
• Further validation is needed for specific target architectures and their unique constraints.