Hardware-Efficient Real-Valued Neural Predistorter for Multimode Power Amplifiers.

Area of Science:

• Electrical Engineering
• Signal Processing
• Telecommunications

Background:

• Digital predistortion (DPD) is crucial for mitigating nonlinear distortion in radio-frequency (RF) power amplifiers (PAs).
• Neural-network-based DPD models offer high accuracy but suffer from complex preprocessing stages.
• Existing methods involve computationally intensive magnitude extraction, phase normalization, and trigonometric operations.

Purpose of the Study:

• To propose a simplified, hardware-efficient DPD formulation for multimode PA linearization.
• To reduce the computational complexity of neural-network-based DPD models.
• To enable practical implementation of advanced DPD techniques on FPGAs and ASICs.

Main Methods:

• A simplified formulation derived from a real-valued three-layer perceptron (TLP)-based DPD model was developed.
• Conventional magnitude/phase normalization was replaced with a simplified feature representation using complex-valued signal products.
• Eliminated square-root, reciprocal, and trigonometric operations.
• Investigated single-network and iterative cascaded network configurations.

Main Results:

• The proposed DPD approach achieved accuracy comparable to the reference model.
• Reduced computational complexity by up to 34% in multiplications and 25% in additions.
• Significantly decreased Look-Up Table (LUT) usage by 73.9%.

Conclusions:

• The simplified DPD formulation offers a hardware-efficient solution for multimode PA linearization.
• The approach maintains high predistortion capability while reducing implementation overhead.
• Suitable for resource-constrained FPGA and ASIC implementations in modern transmitters.