Investigating the impact of irradiation on various ringFET-based SRAM circuits using 3D TCAD

Single-event upsets (SEUs) in Static Random Access Memory (SRAM) can corrupt stored instructions, data, or configuration bits, potentially leading to logic malfunction, system hang, or system reset. Therefore, the investigation of single-event effects is essential for the development of robust and SEU-tolerant memory architectures. In this work, the DC characteristics of junctionless, lightly doped drain (LDD), and Buried Oxide LDD (BOX-LDD) ringFETs are analysed using 3D Technology Computer Aided Design (TCAD) simulations. The BOX-LDD ringFET exhibits improved DC performance compared to both junctionless and conventional LDD ringFET architectures. The operation of the 6T SRAM cell based on these devices is validated, and its Read, Write, and Hold static noise margins (SNMs) are evaluated to assess memory stability for each architecture. Furthermore, SRAM cells based on these devices are examined under radiation exposure using both inner-drain and outer-drain arrangements. The results demonstrate that SRAM cells employing the inner-drain architecture achieve higher critical dose tolerance than those using the outer-drain configuration. In addition, BOX-LDD ringFET-based SRAMs exhibit significantly enhanced radiation robustness compared to SRAMs based on junctionless and conventional LDD ringFETs. Among all the investigated structures, the BOX-LDD ringFET SRAM with the inner-drain design exhibits the highest critical dose tolerance, highlighting its potential for reliable memory applications in radiation-intensive environments such as aerospace and space electronics.