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Role of Si/dielectric interface traps on the reliability of tree-shaped complementary FETs for sub-3 nm technology

S Shreyas Thanthri1, Sresta Valasa2, Venkata Ramakrishna Kotha3

  • 1Manipal Institute of Technology Bengaluru, Manipal Academy of Higher Education, Manipal, India.

Scientific Reports
|June 16, 2026
PubMed

Keywords:
CFETsCMOS inverterInterface densityReliabilitySi/dielectric interfaceSub- 3nm

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