A scalable security co-processor design for IoT applications.

Area of Science:

• Cybersecurity
• Computer Architecture
• Embedded Systems

Background:

• Increasing cyber threats to Internet of Things (IoT) networks necessitate scalable and efficient security solutions.
• Existing cryptographic solutions may lack the flexibility and performance required for diverse IoT applications.
• The RISC-V architecture offers a flexible and open platform for custom hardware development.

Purpose of the Study:

• To propose a novel, efficient, and flexible cryptographic co-processor architecture based on RISC-V for IoT applications.
• To extend the RISC-V architecture to support standard cryptographic algorithms like AES-128 and SHA-256 without custom instruction set modifications.
• To optimize data transfer and minimize pipeline delays for enhanced performance.

Main Methods:

• Designed a RISC-V based cryptographic co-processor with a generic interface for cipher blocks and support for parallel operations.
• Integrated Memory-Mapped I/O (MMIO) and Direct Memory Access (DMA) for efficient data handling.
• Implemented and verified the design on a Xilinx ZCU-102 FPGA board using Vivado 2022.2.

Main Results:

• Achieved high throughput rates: 8.2 Gbps for AES-128 and 482 Mbps for SHA-256 at a 64 MHz clock frequency.
• Demonstrated efficient data transfer without processor pipeline delays.
• Reported a low total power consumption of 1.575 watts.

Conclusions:

• The proposed RISC-V cryptographic co-processor offers a significant improvement in throughput and energy efficiency for IoT security.
• The design's flexibility and avoidance of custom instruction set extensions make it suitable for a wide range of IoT applications.
• This work contributes to developing more secure and performant embedded systems for the evolving threat landscape.