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Published on: January 9, 2014
A Wafer-Level Stacking Scheme Based on Hybrid Etching and Low-Temperature Bonding for High-Performance MEMS Devices
Pengfei Li1,2, Xin Yan2, Yunjie Yang2
1School of Marine Science and Technology, Northwestern Polytechnical University, Xi'an 710072, China.
Micromachines
|June 26, 2026
Summary
This study introduces a novel triple-layer wafer stacking method for advanced 3D MEMS inertial sensors. The new process overcomes limitations in silicon etching and bonding, enabling higher precision and performance in micro-electromechanical systems.
Area of Science:
- Micro-electromechanical Systems (MEMS)
- Materials Science
- Nanotechnology
Background:
- 2D scaling limits MEMS inertial sensor sensitivity and functionality.
- Fabricating complex 3D hollow structures for MEMS faces challenges in deep etching uniformity, corner integrity, and bonding-induced stress.
- 3D stacking architectures are crucial for next-generation high-precision MEMS devices.
Purpose of the Study:
- To propose and validate a triple-layer wafer-level stacking scheme for fabricating high-precision 3D MEMS inertial sensors.
- To address critical fabrication challenges including uniformity in deep silicon etching, wet-etched convex corner integrity, and residual stress from wafer bonding.
- To enable the creation of complex, high-performance 3D hollow structures through an integrated manufacturing approach.
Main Methods:
- A hybrid wet/dry etching technique combined with low-temperature adhesive bonding for triple-layer stacking.
- Implementation of a linear compensation model for precise wet-etched convex corner fabrication.
- Optimization of dry etching uniformity using temporary bonding and plasma flow-field control.
- Development of a low-temperature triple-layer wafer bonding process with precise adhesive dispensing, optical alignment, and controlled curing.
Main Results:
- Successful fabrication of a symmetrically stacked triple-layer MOEMS accelerometer sensing element.
- Achieved a low noise floor of 0.40 µg/√Hz and bias instability of 1.81 µg over 10 minutes.
- Demonstrated improved performance compared to double-layer MEMS devices, validating the proposed stacking scheme.
Conclusions:
- The developed triple-layer wafer-level stacking scheme effectively overcomes limitations in 3D MEMS fabrication.
- This approach enables high-precision manufacturing of complex hollow structures and low-temperature integration for 3D microsystems.
- The methodology offers a viable pathway for advancing high-precision inertial devices and other 3D micro-devices.
