High-Update-Rate Frequency Readout of Sinusoidal Signals for Silicon Resonant Accelerometers Using Digital...

Silicon resonant accelerometers generate sinusoidal outputs with frequency shifts that carry acceleration information. At high update rates, conventional counting-based readout suffers from gate-boundary timing quantization. This work proposes a high-update-rate frequency readout method that reconstructs frequency from the continuous phase evolution of the original sinusoidal resonant signal through quadrature demodulation, phase extraction, and phase difference rather than waveform reshaping and edge counting. To implement the proposed readout chain, an FLL-PLL cooperative loop was included to assist coarse acquisition and fine tracking on a Zynq-7020 platform. This study focuses on the readout principle, FPGA implementation, and prototype-level evaluation. At a 1 kHz update rate, the proposed method showed a lower theoretical quantization limit than the synchronous multi-cycle counting method. Under room-temperature conditions, after a 30 min startup, the proposed method reduced the standard deviation of the 1-second-averaged zero-bias output over 1800-5400 s from 4.1 μg to 2.4 μg and reduced the frequency-difference peak-to-peak value from 0.03743 Hz to 0.02410 Hz. These results support the feasibility and practical value of the proposed method for high-update-rate readout of sinusoidal resonant signals under the tested steady-state conditions.