Reliability-Aware Microsystem Design; Compensation for an Ultra-Low-Power Current-Reuse LC-VCO

Area of Science:

• Electrical Engineering
• Integrated Circuit Design
• Radio Frequency (RF) Engineering

Background:

• Aggressive technology scaling increases manufacturing variations and transistor aging, degrading RF circuit performance, especially in voltage-controlled oscillators (VCOs).
• Micro-electromechanical systems (MEMS) offer performance enhancements but are susceptible to process variations and aging effects impacting transistor parameters.
• Existing VCO designs struggle to maintain stable operation under these reliability challenges.

Purpose of the Study:

• To present an ultra-low-power current-reuse VCO designed for stable performance under process variability and reliability-induced parameter shifts.
• To introduce a self-detecting-correcting (SDC) bias scheme for robust VCO operation.
• To validate the effectiveness of the SDC scheme in mitigating performance drift.

Main Methods:

• Development of an ultra-low-power current-reuse VCO architecture.
• Implementation of a self-detecting-correcting (SDC) bias scheme utilizing body-bias control.
• Derivation of analytical relations for threshold voltage and mobility variations.
• Post-layout simulations in 130 nm CMOS technology and Monte Carlo analysis (500 runs).

Main Results:

• The SDC scheme successfully preserves oscillation frequency, phase noise, and figure of merit (FoM) despite 18% variations in threshold voltage and carrier mobility.
• Mitigation of output amplitude imbalance inherent in conventional current-reuse VCOs.
• Demonstrated low sensitivity to fabrication uncertainty with low standard deviations for phase noise, oscillation frequency, and FoM.
• Achieved -124 dBc/Hz phase noise at 1 MHz offset near 2.4 GHz with ultra-low power consumption (175 μW) from a 0.9 V supply.

Conclusions:

• The proposed SDC bias scheme effectively enhances the robustness of current-reuse VCOs against process variations and aging.
• This approach maintains critical performance metrics like frequency stability and phase noise.
• The design offers a promising solution for reliable and stable RF circuits in advanced CMOS technologies.