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Interface-Engineered, Low-Damage IGZO/HfO₂ Charge-Trapping Memory Devices Fabricated Using a Remote Plasma ALD

Inkook Hwang¹, Hyeonwu Nam¹, Jiwon Kim¹

¹Department of Advanced Materials Engineering, Tech University of Korea, Siheung-si 15073, Republic of Korea.

|June 26, 2026

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Remote plasma processing and annealing optimize indium gallium zinc oxide (IGZO) charge-trapping memory (CTM) transistors. This approach enhances memory window, reduces leakage, and improves stability for next-generation nonvolatile memory applications.

Area of Science:

Materials Science
Electrical Engineering
Semiconductor Physics

Background:

Charge-trapping memory (CTM) transistors are crucial for nonvolatile memory.
Indium gallium zinc oxide (IGZO) and high-k Hafnium dioxide (HfO2) are promising materials for CTM devices.
Plasma processing and annealing significantly impact thin film quality and device performance.

Purpose of the Study:

To develop CTM transistors using IGZO and HfO2.
To investigate the effects of direct plasma (DP) and remote plasma (RP) deposition on HfO2 thin films.
To optimize post-deposition annealing (PDA) conditions for enhanced interfacial stability and device reliability.

Main Methods:

Fabrication of CTM transistors with IGZO channels and HfO2 charge-trapping layers.

Keywords:

HfO2, atomic layer deposition (ALD)IGZO (In–Ga–Zn–O)annealing temperature charge-trapping memory (CTM)crystallization memory window remote plasma (RP)

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Deposition of HfO2 films using atomic layer deposition (ALD) in DP and RP modes.

Post-deposition annealing of IGZO and HfO2 layers at various temperatures.

Main Results:

RP-processed devices showed a wider memory window and reduced gate leakage current compared to DP-processed devices.
RP-processed devices exhibited improved threshold voltage stability.
Post-deposition annealing effectively reduced interfacial defect density and enhanced crystallinity.

Conclusions:

Remote plasma processing is superior to direct plasma processing for fabricating high-performance IGZO CTM devices.
Optimized annealing conditions are critical for enhancing interfacial stability and device reliability.
The choice of plasma process and annealing parameters significantly influences the electrical characteristics of oxide semiconductor-based CTM devices.