Linking device dynamics to neural network performance in ionically gated synaptic transistors

Neuromorphic computing based on artificial synapses requires devices capable of gradual, repeatable, and energy-efficient conductance modulation. Ionically gated transistors are promising candidates because their ion dynamics naturally produce synaptic behavior under low-voltage operation. However, how key device characteristics-conductance range, number of accessible conductance states N, and weight-update nonlinearity β-jointly influence neural network performance remains insufficiently understood. Here, we investigate MoS₂-based ionically gated synaptic transistors using a combined experimental and modeling framework that links device physics to hardware-aware artificial neural network (ANN) simulations across image-classification tasks of varying complexity. We show that under fixed-amplitude pulsing, increasing N introduces a fundamental trade-off: finer weight resolution is accompanied by stronger update nonlinearity. ANN simulations further reveal that, within the nonlinearity range studied here, classification accuracy is governed by a task-dependent optimal weight resolution rather than a simply maximized number of states. To overcome the nonlinear weight updates, we employ a physics-informed transient model to develop a predictive pulse-engineering algorithm and experimentally demonstrate that it can linearize synaptic weight evolution in the same device. These linearized updates improve ANN accuracy by 1.5%-5.2% for MNIST, 4.0%-5.2% for FMNIST, and 1.2%-12% for KMNIST across the tested state numbers, establishing a quantitative link between device-level dynamics and neural network performance in ionically gated synaptic transistors.