Vertically Stacked Indium Gallium Zinc Oxide-Based Three-Dimensional Integrated Circuits

Monolithic three-dimensional (M3D) integration is a promising solution for next-generation integrated circuits, offering enhanced signal propagation, high integration density, and lower fabrication costs than planar architectures. Amorphous oxide semiconductors, with room-temperature deposition capability and large-scale uniformity, are well-suited for 3D applications, yet developing multitier high-performance oxide transistors compatible with traditional technologies remains challenging. Here, we present a threshold voltage modulation strategy for indium gallium zinc oxide (IGZO) transistors via channel thickness control and atomic-layer-deposited surface modification. A four-tier vertically stacked IGZO transistor array has been manufactured with sequential layer-by-layer integration; optimized transistors across the tiers exhibited a low subthreshold swing of 150 mV/dec and an on/off ratio exceeding 108. Combined with via-hole interconnects, we demonstrated functional computing-in-memory 3D circuits featuring inverter modules (tier 1-2) and dynamic random access memory (DRAM) components (tier 3-4). The work advances oxide semiconductors' applications in future advanced 3D circuits.