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Updated: Jul 5, 2026

Experimental Investigation of the Hierarchical Control in DC Microgrids Using a Real-time Simulator
Published on: February 14, 2025
Liquid time constant based neuromorphic active inference for resilient control and health aware battery management in
Arun Kumar Rawat1, Subhash Chandra2, Vinay Kumar Deolia2
1Department of Electrical Engineering, GLA University, Mathura, India. excel.arunrawat@gmail.com.
Abstract:
The transition toward inverter-dominated renewable microgrids is frequently hindered by grid instability and prohibitive battery energy storage system replacement costs. Traditional control strategies often prioritize immediate grid regulation while neglecting electrochemical constraints, which accelerates battery health degradation. This paper proposes a neuromorphic active inference with liquid dynamics (NAI-LD) methodology, a bio-inspired architecture that interprets the microgrid as a dynamical system seeking operational homeostasis. Utilizing continuous-time liquid time-constant neural network, the controller adaptively modulates processing speed, contracting its temporal horizon during disturbances and expanding it during steady state to suppress noise. Evaluated in a simulation environment under severe stochastic transients, the NAI-LD controller restricted frequency excursions to ± 0.025 Hz and total harmonic distortion to a range of 2.3 to 2.7%. By incorporating expected free energy minimization, the framework establishes an intrinsic self-preservation mechanism to reduce daily micro-cycling. Based on the simulated trajectories, techno-economic analysis projects a potential 31.99% reduction in annualized operational expenditure and a theoretical 2.9-year extension of battery hardware lifespan. However, these findings are inherently limited by the simulation environment, the degradation projections are strictly bounded to the semi-empirical characteristics of lithium iron phosphate chemistry and do not currently account for physical communication latencies, sensor noise, or analog-to-digital conversion jitter. While the average algorithm execution time of 0.62 milliseconds indicates computational feasibility for standard digital signal processors, subsequent hardware-in-the-loop experimental validation remains necessary to bridge these modeling limitations and confirm the projected system performance in physical field deployments.
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