Multibit neural inference in a N-ary crossbar architecture

Area of Science:

• Hardware acceleration for artificial intelligence
• Non-volatile memory technologies
• Neuromorphic computing architectures

Background:

• Conventional von Neumann architectures face energy efficiency challenges in AI tasks.
• In-memory computing (IMC) offers a paradigm shift by performing computations directly within memory arrays.
• Crossbar arrays, particularly those using magnetic tunnel junctions (MTJ), are promising for IMC.

Purpose of the Study:

• To present a simulation framework for N-ary crossbar architectures in IMC.
• To evaluate the performance of IMC for neural network inference tasks like XOR and MNIST classification.
• To analyze error sources and optimize N-ary crossbar designs for improved accuracy and efficiency.

Main Methods:

• Developed a simulation framework for N-ary crossbar architectures with minimal implementation assumptions.
• Utilized a simulated (4x4) 4-state magnetic tunnel junction (MTJ) crossbar array.
• Performed XOR and MNIST classification tasks, including PCA dimensionality reduction for performance analysis.
• Investigated the impact of weight quantization, systematic non-idealities, and random noise on MVM accuracy.

Main Results:

• Successfully inferred XOR and MNIST classification tasks using the simulated MTJ crossbar array.
• Achieved 93.56% accuracy on MNIST classification, compared to a 97.56% software baseline.
• Demonstrated that PCA dimensionality reduction significantly reduces operations with only a modest accuracy decrease.
• Identified weight quantization as the primary error source, finding cell-specific random noise less detrimental than systematic errors.

Conclusions:

• The simulation framework provides a viable approach for evaluating N-ary crossbar IMC architectures.
• Weight quantization is a critical factor limiting accuracy in MTJ-based IMC, necessitating careful management.
• Optimal cell state configuration can balance quantization errors and resistance resolution to minimize MVM errors, paving the way for more efficient AI hardware.