Mechanistic evaluation of amorphous InGaZnO-based one transistor-one capacitor memory cell via fast current-voltage...

This study reports the fabrication and analysis of prototype one-transistor-one-capacitor (1T-1C) dynamic random-access memory (DRAM) cells with an amorphous indium-gallium-zinc oxide channel. Fast current-voltage measurements, supported by the H simulation program with integrated circuit emphasis (HSPICE), were used to examine transient charging and discharging operation in a laboratory-scale single-cell structure measured without an integrated sense amplifier. Distinct transient peaks in the measured current-time waveforms allowed for the direct extraction of the charge stored and released from the 1T-1C structure. Retention tests demonstrated that this transient method can monitor charge loss, with the stored charge retained within a loss of ∼1% over hold times of up to 3000 seconds. HSPICE simulations reconstructed the storage node potential (V_S) and reproduced the major transient features, supporting the accuracy of the capacitance network interpretation. The analysis showed that parasitic capacitances within the 1T-1C device deviated the V_S from the bit-line voltage, decreasing the sensing margin. This effect became more pronounced as parasitic capacitances increased for the given storage capacitance. This combined experimental and simulation framework provides a practical method for evaluating charging/discharging behavior and parasitic-coupling effects in prototype AOS-based 1T-1C memory cells.