Analysis and control of a phase-shift parallel switch cell

Increasing the equivalent switching frequency is an important approach to achieving high power density in power converters. However, directly increasing the actual switching frequency (ASF) is limited by the turn-on and turn-off times of semiconductor devices and the associated switching losses. Therefore, a novel phase-shift parallel switch cell (PSPSC) and its control scheme are proposed in this paper. Unlike conventional interleaved converters that employ multiple power-processing phases, the proposed PSPSC is a switch-cell-level structure that replaces only the controllable switch of a conventional converter and sequentially drives the parallel switches, thereby avoiding the current-sharing problem of conventional parallel switch structures. The proposed PSPSC consists of n parallel switches and is used to replace the controllable switch in conventional DC-DC converters, such as buck and boost converters. By evenly allocating the equivalent duty cycle to the n switches and applying 2π/n phase-shifted carrier signals, the proposed control scheme sequentially drives the switches and increases the equivalent switching frequency (ESF) to n times the actual switching frequency (ASF). In the n = 2 experimental prototype, the ESF is increased from 10 kHz to 20 kHz, and the measured inductor current ripple is reduced by approximately 48-51% in the buck and boost converter tests, confirming the predicted ESF multiplication and ripple-reduction effects. These results indicate that the proposed PSPSC can reduce passive-component ripple requirements and distribute device current stress without directly increasing the switching frequency of each semiconductor device.