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DynamiGraph: A Specialized, Runtime-Aware FPGA Overlay for Ultra Low-Latency GNN Inference on Edge Devices
1School of Airspace Science and Engineering, Shandong University, Weihai 264209, China.
Micromachines
|July 28, 2026
Summary
DynamiGraph, an FPGA accelerator, enables ultra-low-latency Graph Neural Network (GNN) inference on edge devices. It achieves significant speedups by optimizing essential computations and exploiting graph sparsity at runtime.
Area of Science:
- Computer Engineering
- Artificial Intelligence
- Edge Computing
Background:
- Graph Neural Networks (GNNs) are crucial for graph data analysis but face challenges in edge deployment due to high computational demands and memory access.
- Resource-constrained edge devices require efficient solutions for real-time GNN inference.
Purpose of the Study:
- To introduce DynamiGraph, a specialized FPGA-based overlay accelerator for ultra-low-latency GNN inference on edge devices.
- To address the limitations of GNN deployment on resource-constrained edge platforms.
Main Methods:
- DynamiGraph utilizes a streamlined architecture focusing on General Matrix Multiplication (GEMM) and Sparse-Dense Matrix Multiplication (SpDMM) kernels.
- A hardware-native runtime optimization mechanism dynamically exploits graph sparsity via an edge-centric execution flow, minimizing redundant computations without static preprocessing.
Main Results:
- Achieved sub-millisecond inference latencies on small-scale benchmarks (e.g., Cora) on an AXU2CGA edge platform.
- Demonstrated a peak throughput of 1467 inferences per second.
- Runtime sparsity exploitation resulted in over 2000x reduction in floating-point operations compared to dense methods.
Conclusions:
- Architectural specialization and runtime awareness offer an efficient approach for real-time graph intelligence in edge environments.
- DynamiGraph provides a viable solution for deploying GNNs on power- and bandwidth-limited edge devices.