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DynamiGraph: A Specialized, Runtime-Aware FPGA Overlay for Ultra Low-Latency GNN Inference on Edge Devices
1School of Airspace Science and Engineering, Shandong University, Weihai 264209, China.
Micromachines
|July 28, 2026
Summary
DynamiGraph, an FPGA accelerator, enables ultra-low-latency Graph Neural Network (GNN) inference on edge devices. It achieves this through specialized hardware and runtime sparsity exploitation, significantly reducing computations for real-time graph intelligence.
Area of Science:
- Computer Science
- Artificial Intelligence
- Hardware Acceleration
Background:
- Graph Neural Networks (GNNs) are crucial for graph data analysis but face challenges in edge deployment due to high computational demands.
- Resource-constrained edge devices struggle with the complexity and memory access patterns of GNNs.
Purpose of the Study:
- To introduce DynamiGraph, a specialized FPGA-based overlay accelerator for ultra-low-latency GNN inference on edge devices.
- To address the limitations of deploying GNNs in edge computing environments.
Main Methods:
- Designed a streamlined FPGA architecture focusing on General Matrix Multiplication (GEMM) and Sparse-Dense Matrix Multiplication (SpDMM) kernels.
- Implemented a hardware-native runtime optimization for dynamic graph sparsity exploitation via an edge-centric execution flow.
- Evaluated performance on an AXU2CGA edge platform.
Main Results:
- Achieved sub-millisecond inference latencies on small-scale benchmarks like Cora.
- Reached a peak throughput of 1467 inferences per second.
- Demonstrated over 2000x reduction in floating-point operations through runtime sparsity exploitation compared to dense methods.
Conclusions:
- DynamiGraph offers an efficient architectural alternative for real-time graph intelligence in power- and bandwidth-limited edge environments.
- Architectural specialization and runtime awareness are key to overcoming GNN deployment challenges on edge devices.