Edge CA-CFAR Data Reduction for Bandwidth-Efficient Real-Time Wideband Spectrum Sensing on Low-Cost SDRs

Real-time wideband radio frequency (RF) spectrum monitoring is increasingly important for unmanned aerial vehicle (UAV) detection and RF surveillance. Low-cost software-defined radio (SDR) networks are attractive but constrained by limited instantaneous bandwidth per node, I/Q data transfer bottlenecks over USB 2.0, and multi-node computational overhead. This paper proposes a bandwidth-efficient FPGA-GPU heterogeneous architecture addressing these limitations. A hardware-efficient cell-averaging constant false alarm rate (CA-CFAR) IP core is deployed on the edge FPGA of each SDR node, forwarding only signal-containing intervals to reduce data transfer volume proportionally to the target duty cycle. Spectra from multiple nodes are stitched into a wideband view and processed in real time via a GPU-accelerated pipeline. The CA-CFAR IP occupies 16.3% of available LUTs with no BRAM and a fixed 10-cycle latency at 100 MHz. Experiments on a five-SDR testbed demonstrate an 88% data transfer reduction at a 10% duty cycle, 376 μs latency from signal acquisition to display-buffer preparation, 96.26% detection probability at -83.16 dBm (SNR ≈ 13 dB), and a 4.5× to 6.0× GPU speedup over CPU processing. These results support real-time wideband RF monitoring on resource-constrained SDR platforms.