Exploring the Feasibility of Deploying Future SDR Applications on RFSoC FPGA Device

Area of Science:

• Electrical Engineering
• Computer Engineering
• Signal Processing

Background:

• Software-defined radio (SDR) is crucial for flexible, programmable communications.
• High-performance SDR systems necessitate careful hardware platform selection.
• Field-Programmable Gate Arrays (FPGAs) offer adaptable hardware solutions for complex signal processing tasks.

Purpose of the Study:

• To implement and evaluate a state-of-the-art Chessboard-based Automatic Modulation Classification (CAMC) algorithm on an FPGA-based RFSoC platform.
• To explore the performance impact of various parallel datapath architectures on the CAMC algorithm.
• To analyze the trade-offs between bandwidth, maximum operating frequency, and resource consumption.

Main Methods:

• Implementation of the CAMC algorithm on an RFSoC FPGA.
• Evaluation of different parallel datapath architectures.
• Analysis of resource utilization (LUTs, FFs) and bandwidth at varying parallel instances and peripheral configurations.

Main Results:

• A parallel CAMC design with peripherals achieved 29.0 GBps bandwidth, consuming 82.31% LUTs and 50.67% FFs.
• A datapath-only design achieved 24.8 GBps bandwidth with lower resource consumption.
• Increased parallel instances led to more High-Performance (HP) ports, decreased maximum operating frequency, and saturated bandwidth growth.

Conclusions:

• The study provides practical reference architectures for FPGA-based SDR systems.
• Open-source hardware designs facilitate evaluation of bandwidth, performance, and resource utilization trade-offs.
• Optimizing CAMC implementation on FPGAs requires balancing performance demands with hardware resource constraints.