A reconfigurable hardware infrastructure for evaluating PUFs in non-volatile memories

Physical Unclonable Functions (PUFs) are widely recognized for deriving strong cryptographic keys from inherent manufacturing variations in hardware. A popular class of PUFs is extracted from memory modules already integrated into computing systems, offering a cost-efficient method for generating strong cryptographic keys. Various techniques exist for extracting PUF responses from such memory modules, including repeated row activation and exploitation of charge leakage effects, known as row hammering, variations in supply voltage, intentional violations of memory timing specifications, as well as the use of random startup values and data retention characteristics. To perform such experiments, especially on novel non-volatile memory modules, a dedicated measurement ecosystem is required, which is presented in this work. The proposed setup uses a custom PCB to connect different types of memories to reconfigurable hardware. An optimized hardware design was developed and deployed on an FPGA, enabling the execution of PUF experiments on various memory modules. The system allows for dynamic adjustment of timing specifications and voltage levels, even during experiment execution. Finally, a program is provided that schedules the experiments, retrieves the results, and enables persistent storage and evaluation methods.