Weight-four parity checks in a spin-shuttling architecture

Area of Science:

• Quantum Computing
• Semiconductor Physics
• Quantum Information Science

Background:

• Sparse semiconductor spin-qubit arrays are promising for quantum processors due to advances in coherent spin shuttling.
• Dynamic, long-range qubit connectivity is crucial for quantum error correction schemes.

Purpose of the Study:

• To demonstrate a silicon spin-qubit device featuring a shuttling bus for coherent qubit transport and interaction.
• To achieve universal control and explore connectivity for quantum error correction protocols.

Main Methods:

• Utilized a silicon spin-qubit device with a shuttling bus and four interaction 'bus stops'.
• Employed coherent qubit shuttling and quantum non-demolition spin measurements for qubit manipulation and control.
• Dynamically populated the array and performed single- and two-qubit operations without charge sensing.

Main Results:

• Achieved universal control of an effective five-qubit processor.
• Demonstrated connectivity for surface-code stabilizer plaquettes with parity checks up to weight four.
• Generated multi-qubit entanglement and reported genuine entanglement of a five-qubit Greenberger-Horne-Zeilinger state.

Conclusions:

• The developed protocols support modular calibration and operation of sparse spin-qubit arrays.
• Highlights the feasibility of near-term quantum error-correction experiments using mobile spin qubits.
• Represents one of the largest entangled states generated with gate-defined semiconductor spins.