High-Mobility and Reliability Ultra-Thin-Channel Oxide Semiconductor Field-Effect Transistors for...

Area of Science:

• Materials Science
• Electrical Engineering
• Semiconductor Physics

Background:

• Oxide semiconductors are promising for monolithic 3D systems, but controlling their properties like carrier mobility and defect density is challenging.
• Existing oxide semiconductor transistors face limitations in defect density, hindering their use in advanced chip technologies.

Purpose of the Study:

• To develop a heterojunction oxide semiconductor channel approach to mitigate interface/channel defect density.
• To engineer a bilayer oxide channel for a memory-logic dual-mode ferroelectric transistor.
• To achieve high performance and reliability in ultra-scaled oxide-based transistors for next-generation applications.

Main Methods:

• Fabrication of a heterojunction oxide semiconductor channel using a bilayer approach.
• Characterization of transistor performance, including field-effect mobility, on-state current, and threshold voltage.
• Assessment of device reliability through gate-bias stress testing and memory endurance measurements.
• Utilizing TCAD simulation (Ginestra) to understand performance improvements.

Main Results:

• Achieved field-effect mobility greater than 100 cm²/V.s, comparable to thin-film silicon.
• Demonstrated a high on-state current of 800 µA/µm at Vd = 1 V with a positive threshold voltage.
• Exhibited excellent reliability with minimal threshold shift (30 mV) after 5000s of stress.
• Showcased robust memory endurance (>10⁷ cycles) and a fast ferroelectric read-after-write delay (180 ns).
• TCAD simulations indicated that a defect self-compensation effect in the bilayer channel enhances performance.

Conclusions:

• The heterojunction oxide semiconductor channel approach successfully mitigates defect density and enhances transistor performance.
• The developed memory-logic dual-mode ferroelectric transistor offers a scalable solution for reliable, high-performance oxide-based electronics.
• This work provides a pathway for next-generation low-power reconfigurable chips, particularly for generative artificial intelligence applications.