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Real-time FPGA prototyping of joint blind equalization with ZF-NL-RSSE for data center interconnects
Optics Letters
|July 31, 2026
Summary
This study introduces a new blind equalization method, zero-forcing nonlinear reduced-state sequence estimation (ZF-NL-RSSE), for high-speed data transmission. It offers improved performance and lower complexity compared to existing techniques.
Area of Science:
- Optical communications
- Signal processing
Background:
- Blind equalization is crucial for high-speed intensity modulation/direct detection (IM/DD) systems in data center interconnects (DCI) due to power efficiency and simplicity.
- Maximum Likelihood Sequence Estimation (MLSE) is theoretically optimal but faces implementation challenges with linear/nonlinear distortions and high complexity.
Purpose of the Study:
- To propose and experimentally demonstrate a novel joint blind equalization scheme for high-speed IM/DD systems.
- To address the limitations of conventional MLSE in handling complex channel distortions and reducing computational load.
Main Methods:
- Development and FPGA implementation of a zero-forcing nonlinear reduced-state sequence estimation (ZF-NL-RSSE) scheme.
- Real-time 80-Gbps Pulse Amplitude Modulation with 4 levels (PAM-4) transmission system over 5-km single-mode fiber (SMF).
Main Results:
- The proposed ZF-NL-RSSE scheme demonstrated rapid blind convergence.
- Achieved superior Bit Error Rate (BER) performance compared to traditional Feed-Forward Equalization (FFE) and Volterra Decision Feedback Equalization (VDFE).
- Performance was comparable to full-state ZF-NL-MLSE with significantly reduced computational complexity.
Conclusions:
- The ZF-NL-RSSE scheme offers an effective solution for blind equalization in high-speed IM/DD systems.
- It provides a practical balance between performance, convergence speed, and implementation complexity.
- This method is suitable for cost-efficient deployment in data center interconnects.
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