AutoFIR: An Automated Framework for Resource-Efficient EEG FIR Filtering on FPGAs

Area of Science:

• Biomedical Engineering
• Computer Engineering
• Signal Processing

Background:

• Wearable electroencephalogram (EEG) processing demands low latency, power, and resource usage.
• Efficient finite impulse response (FIR) filtering is crucial but challenging for field-programmable gate array (FPGA) implementations.
• Current FPGA solutions often lack portability and signal-aware optimization.

Purpose of the Study:

• To present AutoFIR, an automated co-design framework for generating FPGA-based FIR filters for EEG signals.
• To enable high-level EEG filtering specifications to be translated into efficient hardware implementations.
• To address the constraints of latency, power, and resources in wearable EEG processing.

Main Methods:

• AutoFIR integrates signal-aware quantization, shift-add approximation, and architectural optimization.
• A staged design exploration flow uses offline feedback from C-simulations and post-HLS synthesis estimates.
• Candidate designs are screened and compared under memory-access and scheduling constraints.

Main Results:

• AutoFIR generated a DSP-slice-free implementation on a Zynq-7020 platform.
• Achieved a 5.22× latency reduction compared to the unoptimized baseline.
• Maintained filtering fidelity for the evaluated EEG dataset and filter specification.

Conclusions:

• Coordinated, signal-aware automation shows promise for resource-constrained EEG FIR filtering.
• AutoFIR offers an efficient approach to designing hardware for wearable EEG systems.
• The framework facilitates balancing signal fidelity, arithmetic complexity, and hardware parallelization.