AutoFIR: An Automated Framework for Resource-Efficient EEG FIR Filtering on FPGAs

Real-time electroencephalogram (EEG) processing on wearable platforms faces strict latency, power, and resource constraints, making efficient finite impulse response (FIR) filtering a critical challenge. Many representative field-programmable gate array (FPGA) solutions rely on manual design or vendor-supplied intellectual property (IP) cores, which can limit portability and signal-aware optimization across different signal specifications. This work presents AutoFIR, an automated co-design framework that translates high-level EEG filtering specifications into FPGA-based FIR implementations. AutoFIR integrates signal-aware quantization, shift-add approximation, and systematic architectural optimization to balance signal fidelity, arithmetic complexity, and hardware parallelization. Offline feedback from C-simulations and post-HLS synthesis estimates is used to screen and compare candidate designs within a staged design exploration flow under memory-access and scheduling constraints. On the evaluated Zynq-7020 platform, AutoFIR generates a DSP-slice-free implementation that achieves a 5.22× latency reduction over the unoptimized baseline while maintaining filtering fidelity under the current EEG dataset and filter specification. These results suggest that coordinated, signal-aware automation is promising for the evaluated resource-constrained EEG FIR filtering scenario.