An entangling gate for dual-rail erasure qubits

Area of Science:

• Quantum Computing
• Quantum Error Correction

Background:

• Quantum error correction (QEC) is crucial for quantum computing but demands low physical qubit error rates and significant hardware overhead.
• Engineering qubits with a strong error hierarchy, where common noise is easily correctable, can alleviate these demands.
• Erasure qubits offer this advantage by prioritizing correctable leakage errors over residual Pauli errors, leading to higher thresholds and better scaling.

Purpose of the Study:

• To design and experimentally realize a two-qubit entangling gate for dual-rail cavity qubits, a type of erasure qubit.
• To verify the preservation of the error hierarchy during gate operations.
• To assess the gate's speed, erasure rates, Pauli errors, and error bias.

Main Methods:

• Designed a two-qubit entangling gate for dual-rail cavity qubits, which are superconducting microwave cavity-encoded erasure qubits.
• Experimentally demonstrated the gate's performance, focusing on error hierarchy preservation.
• Quantified gate speed, erasure rates, Pauli error rates, and the bias towards dephasing errors.

Main Results:

• The designed two-qubit gate largely preserves the error hierarchy of the dual-rail cavity qubits.
• The gate operates quickly (approx. 500 ns) with low erasure rates (~0.5%) and low Pauli errors (<0.1%).
• A strong bias towards dephasing errors was observed, with bit-flips effectively suppressed to the 10^-6 level.

Conclusions:

• The developed two-qubit gate effectively maintains the error hierarchy of erasure qubits.
• These findings pave the way for faster implementation of scalable, error-corrected quantum computing systems.
• Surface code simulations support the potential for rapid error suppression with this approach.