A Polycrystalline Silicon Thin-Film Transistor with Grain-Induced Stochasticity for an Energy-Efficient True Random...

For more than seven decades, the metal oxide semiconductor field-effect transistor (MOSFET) has been primarily exploited as a switch and an amplifier. Nevertheless, its capability to function as an oscillator has received little attention. Whether polycrystalline silicon thin-film transistors (poly-Si TFTs), which contain grain boundaries and associated trap states, can temporarily retain carriers despite the high recombination rates within these regions, remains an unresolved long-standing question. To address these issues, we demonstrate abnormal stochastic oscillation based on a single transistor latch (STL) in poly-Si TFTs. Here, we utilize the abnormal and unpredictable stochastic oscillation of a poly-Si-TFT-based cryptographic transistor (cryptosistor) as an entropy source. While STL phenomena and STL-driven oscillations have typically been explored in single-crystalline silicon on expensive silicon-on-insulator (SOI) wafers, their implementation in poly-Si TFTs has been hindered by grain-boundary traps, which promote hole recombination and suppress the body-potential buildup required for STL operation. To overcome this challenge, we optimized the poly-Si deposition and annealing conditions to enlarge the average grain size and adjusted the body doping concentration to facilitate hole accumulation. As a result, STL and STL-based oscillations were successfully achieved in monolithic three-dimensional (3D) stackable poly-Si TFTs. Moreover, unlike single-crystalline devices, the presence of grain-boundary traps introduces stochastic carrier trapping and detrapping, thereby amplifying the randomness of the oscillation. Leveraging this grain-enhanced entropy characteristic, we realized a compact and energy-efficient true random-number generator (tRNG) with full CMOS compatibility. The proposed poly-Si TFT-based tRNG passed all 15 randomness tests of the NIST Special Publication 800-22 suite, exhibiting a high energy efficiency of 0.21 pJ/bit. Additionally, this tRNG is robust to iterative operational stresses and ambient temperature changes. The proposed approach inherently supports 3D monolithic stacking, enabling seamless integration on top of the existing CMOS circuitry for advanced hardware systems.