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A Universal van der Waals Tunneling Injector for Monolayer CMOS
Hanbin Cho1, Jing Huang2, Seonguk Yang1
1Department of Chemical and Biomolecular Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Republic of Korea.
Advanced Materials (Deerfield Beach, Fla.)
|August 12, 2026
Summary
Degenerately doped tin diselenide (SnSe2) acts as a universal van der Waals injector for two-dimensional (2D) semiconductors. This enables efficient, polarity-tailored tunneling for high-performance, low-power 2D integrated circuits.
Area of Science:
- Materials Science
- Condensed Matter Physics
- Nanotechnology
Background:
- Two-dimensional (2D) semiconductors offer potential for atomic-thickness logic devices.
- Monolayer complementary metal-oxide-semiconductor (CMOS) faces challenges due to polarity-dependent contacts and thermionic emission.
- A unified injection solution for both p-type and n-type channels is lacking.
Purpose of the Study:
- To introduce a novel, degenerately doped crystalline tin diselenide (SnSe2) as a universal source-side van der Waals (vdW) injector.
- To enable all-tunneling carrier injection into both p- and n-type monolayer 2D semiconductor channels.
- To overcome limitations of conventional contacts and advance 2D integrated circuit performance.
Main Methods:
- Utilized degenerately doped SnSe2 with high electron affinity (~5.1 eV) and carrier density (>10^19 cm^-3).
- Investigated SnSe2's interfacial coupling with WSe2 (p-type) and MoS2 (n-type) monolayer channels.
- Analyzed tunneling mechanisms including band-to-band tunneling and Fowler-Nordheim-like tunneling.
Main Results:
- Achieved over 1000-fold drive current enhancement in p-type WSe2 via type-III alignment and band-to-band tunneling.
- Demonstrated a >10^9 on/off ratio and sub-70 mV/dec subthreshold swing in n-type MoS2 through gate-tunable injection.
- Fabricated a monolayer CMOS inverter with a maximum voltage gain of ~340.
Conclusions:
- Degenerate SnSe2 functions as a dual-polarity vdW injector for 2D materials.
- This approach suppresses interfacial states and enables polarity-tailored tunneling.
- Provides a pathway for developing high-performance, low-power 2D integrated circuits.
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