Time-Aware and Power-Law Retention Gating Mechanisms in LSTMs for Irregularly Sampled Sensor Data: A Survey

Sensor data streams from Internet of Things devices, wearables, and monitoring systems are often irregularly sampled due to variable transmission intervals, intermittent connectivity, and event-driven reporting, producing heavy-tailed temporal gaps between observations. Long Short-Term Memory (LSTM) networks, widely used for sequential sensor data analysis, assume a synchronous, equidistant timeline and regulate memory through a forget gate whose dynamics are input- and state-dependent but carry no explicit dependence on elapsed real time. Under stationary inputs, the standard LSTM architecture additionally exhibits a structural bias toward exponential memory decay. However, in real-world sensing contexts, uneven sampling and long-range dependencies are common, violating both assumptions simultaneously. To address this, we survey and taxonomise two independently proposed strategies: time-aware mechanisms that rescale memory using elapsed time, and power-law retention schemes that model slower, heavy-tailed forgetting. Through comparative analysis, we demonstrate that both strategies converge on the same underlying failure point, the inability of the forget gate to jointly adapt its attenuation rate and decay profile to temporal context and sensor input, and frequently employ functionally redundant mechanisms. We subsequently articulate a unified design framework that defines the essential properties that temporal forget gates must satisfy to enable robust learning from irregular sensor streams. These findings indicate that future sequence models for sensing applications should jointly integrate temporal-gap awareness with adaptive retention dynamics to better capture complex temporal dependencies in real-world environments.