System-Level Integration and Evaluation of an APS-SoC-Based Electrical Resistance Tomography Measurement System

This study presents and evaluates a system-level optimization of an electrical resistance tomography (ERT) measurement platform based on a ZYNQ-7020 all-programmable system-on-chip (APS-SoC). The design combines deterministic programmable-logic (PL) acquisition, processing-system (PS) configuration and communication scheduling, AXI/DMA data movement, Gigabit Ethernet transmission, and a seventh-order Butterworth excitation filter. FFT-based amplitude extraction and Tikhonov reconstruction remain on the host computer so that the reconstruction algorithm and regularization settings remain identical for the baseline and proposed systems; the present prototype is therefore not claimed as a fully standalone smart sensor. Under the same 16-electrode tap-water testing configuration, the average frame rate increased from 58.23 ± 1.88 FPS to 123.02 ± 1.62 FPS (mean ± sample standard deviation, n = 10), end-to-end latency decreased from 5.2 ms to 2.1 ms, SFDR increased from 68 dB to 95 dB, and SSIM increased from 0.72 to 0.94. In one representative static hardware record at 160 kHz, the calculated amplitude-stability SNR values were 65 dB and 100 dB for the baseline and proposed excitation paths, respectively, while total harmonic distortion decreased from 15.2% to 7.5%. These single-condition signal quality values are descriptive rather than uncertainty-bounded performance specifications. The image-quality differences are attributed primarily to cleaner boundary-voltage measurements with an unchanged reconstruction method, whereas the frame-rate gain reflects the combined PL/PS data path and Gigabit Ethernet upgrade.