Related Experiment Video
Updated: Aug 15, 2026

Building a Simple and Versatile Illumination System for Optogenetic Experiments
Published on: January 12, 2021
Buried p-type GaN activation under V-pitted n-type GaN for tunnel junction micro-LEDs
Abstract:
Tunnel junctions (TJs) provide an alternative electrode architecture for GaN-based micro-light-emitting diodes (μ-LEDs) by replacing conventional p-type contacts with highly conductive n-type GaN layers. However, their performance is often limited by incomplete activation of Mg acceptors in buried p-type GaN after the thermal annealing process, which increases resistivity and degrades tunneling efficiency. In this work, we investigate a V-pitted n-type GaN structure grown on a TJ and its impact on the activation of buried p-type GaN and TJ. Compared with a flat n-type GaN reference (Flat μ-LED), the V-pitted structure (VP μ-LED) exhibits enhanced optical performance. For 20 × 20 μm2 VP μ-LEDs, the integrated EL intensity increases by approximately 1.35 times at 5 A/cm2, while the optical output power increases by 1.3 times at 30 mA/cm2 compared with the Flat μ-LED. Electrical characterization shows that the forward operating voltage improves from 5.46 V to 3.48 V at 200 μA. At -15 V, the reverse leakage current is significantly reduced, shifting from the 10-10-10-7 A range in the Flat μ-LED to the 10-12-10-10 A range in the VP μ-LED, along with a much narrower statistical distribution. The effective series resistance is also reduced from 2.77 kΩ to 1.66 kΩ. Structural analysis shows that V-pits form nanoscale vertical channels penetrating the overgrown n-type GaN layer toward the buried p-type GaN region. These channels, with a characteristic width of ∼12 nm, are significantly larger than the kinetic diameter (∼0.289 nm) of H2, providing an effective out-diffusion pathway for H2 gas during activation annealing. This promotes more effective and spatially uniform activation of the buried p-type GaN and TJ, resulting in reduced leakage, improved carrier transport, and enhanced device performance.
Related Concept Videos
Biasing of P-N Junction
In equilibrium, no external voltage is applied across the p-n junction. The depletion region is formed at the junction interface due to the diffusion of carriers, which leaves behind charged dopants, acceptors on the p-side, and donors on the n-side. These immobile charges create an electric field that prevents further diffusion of carriers. The related energy band...
Bipolar Junction Transistor
The structure...
P-N junction
MOSFET: Enhancement Mode
In their basic form, enhancement-mode MOSFETs are typically non-conductive when the gate-source voltage (Vgs) is zero. This default 'off' state means no current...
Biasing of FET
In an N-channel JFET, the structure consists of N-type material forming the channel on a P-type substrate, with the gate...
Biasing of Metal-Semiconductor Junctions
In Schottky junctions, where the semiconductor is n-type, applying a positive voltage to the metal relative to the semiconductor reduces its Fermi...

