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A Review on Emerging High-k Dielectrics for Charge Trapping Memory: Fundamentals, Fabrication, Modification and
Huan Niu1, Mengwen Fan1, Lin Lv1
1Hubei Yangtze Memory Laboratories, School of Integrated Circuits, Hubei University, Wuhan, P. R. China.
None:
Charge trapping memory (CTM) has garnered significant attention as a pivotal alternative for next-generation flash memory cells, with its merits rooted in core high-k dielectric materials. However, the limited charge trapping density and shallow trap depth of intrinsic high-k dielectric materials directly result in unsatisfactory storage efficiency. Numerous studies have been conducted on the performance optimization of high-k dielectric materials as charge trapping layers (CTLs) for CTM, yet the working mechanisms of various current modification strategies are scattered, and there is a lack of systematic investigation and summary. Herein, this article presents a comprehensive review of the recent progress of high-k dielectric materials in CTM, which specifically covers four aspects: fundamentals, fabrication, modification strategies, and cutting-edge applications, and aims to provide valuable theoretical references and technical guidance for research and development of novel high-k dielectric materials and related electronic devices.
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