Surface code scaling on heavy-hex superconducting quantum processors

Demonstrating subthreshold scaling of a surface-code quantum memory on hardware whose native connectivity does not match the code remains a central challenge. We address this on IBM heavy-hex superconducting processors by co-designing the code embedding and control: a depth-minimizing SWAP-based "fold-unfold" embedding that uses bridge ancillas, together with robust, gap-aware dynamical decoupling (DD). We show that anisotropic scaling from distance 3 to (d_x = 3, d_z = 5) and (d_x = 5, d_z = 3) improves protection of Z- and X-basis logical states, respectively, and a calibrated  ~ 30% noise reduction would enable isotropic (5, 5)-versus-(3, 3) scaling on this heavy-hex layout. We show that DD suppresses coherent ZZ crosstalk and non-Markovian dephasing during idle gaps, eliminating spurious subthreshold claims. To quantify performance, we derive an entanglement fidelity metric which reveals that widely used single-parameter suppression-factor fits can mischaracterize code performance. Our results provide a path to robust subthreshold surface-code scaling through optimized DD on non-native architectures.