Optimization and hardware evaluation of a modified reconfigurable ring oscillator PUF

Physical Unclonable Functions (PUFs) are emerging hardware security primitives that generate device-specific secret keys by exploiting inherent manufacturing variations. Among the various PUF architectures, Ring Oscillator PUFs (RO-PUFs) are notable for their simplicity and high performance. However, conventional RO-PUFs suffer from a limited number of challenge-response pairs (CRPs), making them susceptible to machine learning (ML) attacks, and scaling them to handle more CRPs often incurs significant hardware overheads. This paper presents a novel Configurable Delay Unit based Modified Reconfigurable Ring Oscillator PUF (MRROPUF) that integrates Exclusive-OR (XOR) and Exclusive-NOR (XNOR) gates to dynamically configure delay paths using challenge bits. This architecture substantially increases the CRP space and entropy while reducing resource utilization. Additional security is achieved through challenge obfuscation via permutation and enhanced reliability via Temporal Majority Voting (TMV). The proposed design was implemented on Xilinx Virtex-6 and Zynq-7000 FPGAs. The experimental results demonstrated high uniqueness (49.76% and 49.0%), near-ideal uniformity (49.3% and 49.0%), and excellent reliability (99.72% and 99.0%) across the two platforms. Compared to existing Configurable RO-PUF and Reconfigurable RO-PUF designs, the MRROPUF achieves superior efficiency and robustness, making it a strong candidate for secure and lightweight hardware authentication in resource-constrained applications.