Stage-Complete Mapping of Pairwise Monocular Structure-from-Motion to Field-Programmable Gate Arrays

This paper presents a stage-complete programmable-logic architecture for pairwise monocular structure from motion using calibrated, pre-undistorted 1920 × 1080 video. It integrates streaming feature extraction, Block-RAM-backed Top-K selection, spatial-bucket matching, two-pass essential-matrix estimation and pruning, fixed-point pose recovery, and triangulation with point-coordinate output. Bounded feature storage, local correspondence search, and mixed floating- and fixed-point arithmetic support the complete pairwise chain without processor-side geometry computation. The complete VCU118/XCVU9P design was synthesized, placed, routed, and compiled to a bitstream in Vivado 2026.1, meeting setup and hold timing with +0.031 ns and +0.010 ns slack, respectively. It uses 12.09% of the device's logic lookup tables and 32.94% of its Block RAM tiles. Controlled numerical tests characterize the operating domain of the geometry stages. The cycle-based model estimates a 13.13 ms geometry-back-end subtotal at 1000 matches; 60 fps is the architectural input target. To the authors' knowledge, within the directly comparable literature surveyed, this is the first reported stage-complete mapping of the listed pairwise chain entirely to programmable logic.