Design, Simulation, and Experimental Characterization of a Superimposed Top- and Bottom-Gate Field-Emission Triode...

This study presents a comprehensive experimental and theoretical investigation into dual-gate field-emission devices fabricated using a standard 0.35 µm CMOS-MEMS process. Two emitter configurations, the concave-tip and triangular-tip, are characterized, and their performance is rigorously analyzed using three-dimensional simulations based on Fowler-Nordheim emission theory. To account for discrepancies between initial designs and fabricated devices, the influence of critical geometric parameters, including tip apex radius, cathode-anode spacing, and tip sharpness, is systematically evaluated regarding emission current and threshold voltage. Compared to the floating-gate baseline (~38 V), dual-gate (DG) operation lowers the threshold voltage by ~70% (~10 V), enhances low-voltage emission over tenfold, and provides a 3.4-fold boost in differential output conductance. Simulation analysis indicates this improvement stems from enhanced electrostatic field distribution governed by the gates. Furthermore, the top gate, due to its proximity to the emitter tip relative to the bottom gate, provides superior control over emission current at lower operating voltages. Three-dimensional simulations corroborate these findings, revealing that minimizing both the tip radius and cathode-anode spacing substantially enhances tunneling electron flow. Additionally, gate voltage sweeps confirm that electron trajectories are effectively directed by electrostatic steering. These findings establish critical design guidelines for integrating field-emission devices into standard CMOS platforms, facilitating the development of on-chip electrostatically controlled electron sources for integrated vacuum microelectronics.