A Dual-Programmable 2M NOR Flash Architecture for Energy-Efficient In-Memory Computing

Conventional NOR Flash architectures employ either a 1M structure or a 1T-1M structure, the latter integrating an access transistor to enable selective program and erase operations. While the access transistor occupies a substantial portion of the 1T-1M cell area, it does not contribute to information storage. Here, a 2M NOR Flash architecture is demonstrated in which two series-connected charge-trap transistors ( ${\mathrm{Cell}}_1$ and ${\mathrm{Cell}}_2$ ) simultaneously function as programmable memory elements and current-controlling components, enabling conductance-window extension and current-path gating within a single device structure. Device measurements show that sequential programming of the two memory devices significantly extends the accessible current window, reducing the minimum read current from 72.7 nA to 4.22 pA while maintaining reliable inhibit behavior under array bias conditions. Hardware-aware neural inference further demonstrates that the extended conductance window reduces inference power by approximately 45% across multiple neural networks. In addition, the second programmable memory device enables true-off hardware pruning and ${\mathrm{Cell}}_2$ state modulation, allowing substantial reduction of inference power while maintaining classification accuracy. These dual functional roles establish a task-adaptive operation framework, in which the proposed 2M NOR Flash architecture serves as a scalable device platform for energy-efficient compute-in-memory systems.