Hardware Acceleration of Stochastic Neural Networks Enabled by Bit-Cell Level Co-Design of Magnetic Tunnel Junctions

Processing-in-memory architectures mitigate data shuttling bottlenecks in deterministic AI workloads, but still depend on costly external entropy sources for probabilistic models. Here, we present a magnetic-tunnel-junction-based processing-in-memory architecture that unifies data storage and massively parallel probabilistic computation for stochastic and deterministic neural networks. By introducing bit-paired stochastic and stable magnetic tunnel junctions, we realize a multi-precision stochastic memory cell that transduces stored binary weights into variance-tunable stochastic bitstreams in situ. We evaluate the architecture's versatility across three progressive regimes of stochastic neural computation. First, by using a hardware-in-the-loop prototype interfacing fabricated stochastic spin-orbit torque magnetic tunnel junctions with a field-programmable gate array chip, we validate stochastic matrix-vector multiplications and achieve near-floating-point accuracy without specialized retraining. Second, for networks with stochastic neurons, we demonstrate an Ising machine that utilizes adaptive-precision sampling and dynamic graph routing to reduce time-to-solution. Third, we propose an in-memory Bayesian computer with independent control of weight means and uncertainties, and apply it to a localization problem under unreliable inputs. By keeping intermediate signals in the stochastic domain, the architecture reduces peripheral overhead associated with random-number generation and data conversion. This device-circuit co-design provides a shared hardware platform for stochastic neural inference, combinatorial optimization, and uncertainty-aware computing.