Breaking the Drivability-Threshold-Voltage Trade-off in 40 nm Vertical Gate-All-Around Oxide FETs via Spacer-Defined...

Spacer-defined offset engineering is presented as a structural strategy to enhance the on-state current (ION) of vertical gate-all-around (VGAA) amorphous indium-gallium oxide (IGO) field-effect transistors (FETs) while preserving threshold-voltage (VTH) control. Increasing the indium fraction in the IGO channel improved ION but simultaneously caused a pronounced negative VTH shift, revealing an observed trade-off in composition-based channel engineering. To circumvent this limitation, the SiO2 spacer thickness was scaled from 100 to 30 nm while maintaining the optimized IGO 6:3 channel composition. For IGO FETs with a gate length of 40 nm, the average ION increased from 1.24 ± 0.54 to 9.5 ± 1.94 μA as the spacer thickness was reduced from 100 to 30 nm, without inducing a negative VTH shift. For twenty 30-nm-spacer devices, the average VTH and subthreshold swing were 0.29 ± 0.05 V and 71.4 ± 4 mV/dec, respectively, with an apparent drain-induced barrier lowering (DIBL) factor of 3.7 mV/V. Y-function analysis, temperature-dependent measurements, and Technology Computer-Aided Design (TCAD) simulations revealed that the performance enhancement originated from reduced access resistance and electrostatic modulation of the source-side access region, while no statistically distinct spacer-dependent change in the effective source-side injection barrier was resolved. The optimized device also exhibited VTH shifts of only +79 and -26 mV under positive and negative bias-temperature stress, respectively, at 95 °C for 3600 s under effective gate fields of ±3 MV/cm, while the VGAA-based two-transistor zero-capacitor dynamic random-access memory (2T0C DRAM) cell exhibited a retention time exceeding 100 s. These results establish spacer-defined offset engineering as an effective structural design approach for oxide-semiconductor memory transistors that require both high ION and stable VTH operation.