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Updated: Oct 10, 2026

Optimized Fabrication Procedure for High-Quality Graphene-based Moiré Superlattice Devices
Published on: July 11, 2025
Wafer-scale low-symmetry graphene moiré superlattice for integrated quantum rectifiers
Wenhao Tan1,2, Jiuming Liu3, Zhenhao Gong4
1State Key Laboratory of Materials for Integrated Circuits, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai, China.
Abstract:
Low-symmetry materials unlock rich Berry curvature physics and anomalous transport phenomena that are forbidden in high-symmetry quantum systems through rigorous crystalline symmetry constraints. Current approaches rely on external fields or complex heterogeneous stacking to break crystalline symmetries, which hinders scalable device integration. In this work, we demonstrate surface premelting engineering to create wafer-scale low-symmetry graphene on germanium-110 [Ge(110)]. Controlled premelting forms striped germanium surface patterns that reduce graphene symmetry from D6h to C1v, producing a room-temperature nonlinear Hall conductivity of ~11 micrometers per volt per ohm. First-principles calculations attribute this to originating from overtilted massive Dirac cones of hybridized germanium bands and the graphene Dirac cone. Integrated nonlinear Hall rectifiers generate >20 millivolts of output from radio frequency input and drive commercial voltage boosters and light-emitting diodes, establishing a complementary metal-oxide semiconductor-compatible route toward wafer-scale nonlinear quantum devices.

